The accurate reproduction of patterns on the surface of a semiconductor substrate is critical to the proper fabrication of semiconductor devices. The semiconductor substrate may have undergone previous fabrication processes and may already feature layers and structures created by those fabrication processes. Improperly reproduced patterns can result in semiconductor devices that do not operate to design specifications or that do not operate at all. For example, transistors can be created with improperly sized gates; conductors can be created that are short circuited or open circuited with other conductors or devices; structures can be created with wrong geometries, and so forth. Improperly reproduced patterns can reduce the yield of the fabrication process, thereby increasing the overall cost of the product. The reproduction process typically involves the use of optical lithography to reproduce the patterns onto the surface of the semiconductor substrate followed by a variety of processes either to subtract (for example, etch) or to add (for example, deposit) materials from and to the semiconductor substrate.
However, as the dimensions of the structures making up the patterns continue to become smaller, their sizes approach the wavelengths of the light used in optical lithography. Interference and processing effects can cause distortion and deviation in the mask's patterns as they are reproduced onto the semiconductor substrate. One cause of such pattern deviation is associated with the difficulties of locally exposing regions of the semiconductor wafer to the correct amount of light at each individual local region during fabrication. Exposure settings (i.e. focus and dose) needed to adequately expose a particular region on a wafer are typically dependent on the feature density of the particular region's local geometry. If any region of the wafer is incorrectly exposed to the light passing though the mask, regions of the photosensitive resist may be overexposed or underexposed which will lead to device failure. Unfortunately, as device geometries shrink, an exposure setting that may be suitable for one particular region of the wafer with a particular feature density may overexpose or underexpose another region of the wafer with a different feature density, thereby making it impossible to expose the wafer in a single mask exposure.
In the field of small, densely packed applications using small geometry transistors, what is needed is a mask method and structure that can optimally expose all critical dimension regions of varying densities.